This invention relates to semiconductor packaging.
Portable electronic products such as mobile phones, mobile computing, and various consumer products require higher semiconductor functionality and performance in a limited footprint and minimal thickness and weight at the lowest cost. This has driven the industry to increase integration on the individual semiconductor chips.
In one approach to increase functionality and performance in packages, integration is implemented on the “z-axis,” that is, by stacking chips, and stacks of up to seven chips in one package have been used. This provides a dense chip structure having the footprint of a one-chip package, and obtaining thicknesses that have been continuously decreasing. The cost of a stacked die package is only incrementally higher than the cost of a single die package and the assembly yields are high enough to assure a competitive final cost as compared to packaging the die in individual packages.
A practical limitation to the number of chips that can be stacked in a stacked die package is the low final test yield of the stacked-die package. Inevitably some of the die in the package will be defective to some extent, and therefore the final package test yield will be the product of the individual die test yields, each of which is always less than 100%. This can be particularly a problem even if only two die are stacked in a package but one of them has low yield because of design complexity or technology.
Another approach to integrating on the “z-axis” is to stack die packages to form a multi-package module. Stacked packages can provide numerous advantages as compared to stacked-die packages. Examples of conventional stacked ball grid array packages are described, for example, in the background of U.S. Pat. No. 7,064,426.
For instance, each package with its die can be electrically tested, and rejected unless it shows satisfactory performance, before the packages are stacked. As a result the final stacked multi-package module yields are maximized.
Each die or more than one die can be packaged in a respective package in the stack using the most efficient first level interconnect technology for the chip type and configuration, such as wire bonding or flip chip, to maximize performance and minimize cost.
The z-interconnect between packages in a stacked multi-package module is a critical technology from the standpoint of manufacturability, design flexibility and cost. Z-interconnects that have been proposed include peripheral solder ball connection. The use of peripheral solder balls for z-interconnects in stacked multi-package modules limits the number of connections that can be made and limits design flexibility, and results in a thicker and higher cost package.
FIG. 1 is a diagrammatic sketch in a sectional view illustrating the structure of an example of a conventional multipackage module, generally known as a “package-on-package” assembly, in which z-interconnection between the stacked packages is made by solder balls. A first package (the “bottom” package) in this example may be a conventional ball grid array package, including a die mounted upon a die attach surface of a “bottom” package substrate 12 using a die attach adhesive. The bottom package substrate has at least one metal layer (two are shown in the example illustrated in FIG. 1). The bottom package die is electrically connected to the bottom substrate by wire bonds, and the bottom package die and the wire bonds are enclosed in a mold cap. The bottom package substrate is electrically interconnected to circuitry, such as for example, a motherboard (not shown) in the device in which the package is deployed, in this example by second-level interconnect solder balls 18. A second package (the “top” package) in this example includes two die mounted one over the other and affixed upon a “top” package substrate 14 using a die attach adhesive. The bottom package substrate has at least one metal layer (two are shown in the example illustrated in FIG. 1). The top package die are electrically interconnected to the top substrate by wire bonds, and the die attach surface of the top substrate and all the structures mounted upon it are encapsulated. Thus in this example the top package is stacked on the bottom package and is similar in structure to the bottom package, except that the z-interconnect solder balls 16 in the top package are arranged at the periphery of the top package substrate 14, so that they effect the z-interconnect without interference of the top package substrate with the mold cap of the bottom package.
Solder masks are patterned over the metal layers at the surfaces of the substrates 12, 14 to expose the underlying metal at bonding sites for electrical connection, for example the wire bond sites and bonding pads for bonding the wire bonds and solder balls.
The z-interconnection in the package-on-package module of FIG. 1 is achieved by reflowing the solder balls 16 attached to peripheral bonding pads on the lower metal layer of the top package substrate 14 onto peripheral bonding pads on the upper metal layer of the bottom package substrate 12. In this configuration the distance h between the top and bottom packages must be at least as great as the mold cap height of the bottom package, which (depending among other factors upon the thickness of the bottom package die and the flow characteristics of the molding material) may be 0.3 mm or more, and typically is in a range between 0.5 mm and 1.5 mm or more. The z-interconnect solder balls 16 must accordingly be of a sufficiently large diameter that when they are reflowed they make good contact with the bonding pads of the bottom substrate; that is, the z-interconnect solder ball diameter must be greater than the encapsulation height. A larger ball diameter dictates a larger ball pitch, which in turn limits the number of balls that can be fitted in the available space, limiting the number of z-interconnections that can be made between the packages. A greater number of balls at a given pitch can be accommodated by adding additional rows of balls; but this requires dedicating additional substrate area to the z-interconnection, and for a given bottom package die size this results in an increase in package footprint. The problem is exacerbated where the bottom package includes two or more stacked die, as additional die add to the overall mold cap thickness. For some bottom package configurations, a conventional package-on-package configuration using peripheral solder ball z-interconnection may be impracticable.